The invention pertains to electrically programmable (reprogrammable) semiconductor memories.
To increase the total manufacturing yield, such memories comprise redundant row or columns which, upon determination of faulty rows or columns, that is, of rows or columns which are found to have at least one faulty memory cell, take the place of the faulting rows or columns, provided that these redundant rows or columns themselves have been ascertained as not being faulty. Since, in the present case, a row redundance is more effective than a column redundance, because rows are more likely to fail than columns, the invention will be described in the following with reference to the row redundance which, however, is not meant to imply any restriction.
For explaining the problem of the memory redundance reference is made to the technical journal "Electronics" of July 28, 1981, pp. 117 to 133. In implementing semiconductor memories having redundance it is common practice to use redundance decoders which are programmed in particular by employing connections capable of being split. Relative thereto, reference is made, for example, to the "IBM Technical Disclosure Bulletin", 18/6 (November 1975), pp. 1777 and 1778, the "1980 IEEE International Solid State Circuit Conference. Digest of Technical Papers", pp. 146 and 147, as well as to the European Patent Appln. EP-A2-83 212. In these semiconductor memories having redundance, the programming of the redundance decoders, in the course of which faulty rows are excluded and unobjectionable rows are inserted, is carried out during the final measurement following fabrication.
An integrated matrix memory of the type to which the invention is directed is disclosed in EP-A1-86 905. The memory comprises m times n nonvolatile reprogrammable memory cells within a first partial area of the memory and, includes spare rows (redundant rows) of a spare memory which, instead of defective rows of the main memory, are capable of being selected via a spare decoder (redundance decoder), with the addresses of the defective rows being filed as data in a second intact partial area of the matrix memory. In this conventional type of matrix memory the data outputs thereof are connected to the data inputs of the correction register, with these data inputs, in response to a data transfer signal from a control stage, for initiating the read operation and for transferring or taking over the data from the second partial area, receiving the addresses of the defective cells. These addresses prevent the spare decoder from writing the data into the faulty rows of the main memory and cause it, instead, to write them into associated rows of the spare memory, in the course of which the decoder of the main memory, via a blocking input, receives a blocking signal from the spare decoder.
During operation of the conventional matrix memory, either at the end of each process of turning on the supply or operating voltage, or else upon deviation of the supply or operating voltage from a nominal value, a reset cycle is initiated in the course of which only the addresses of the second area are read out and taken up into the correction register.
In the conventional type of integrated matrix memory having redundant spare rows or else also spare columns and in accordance with the measuring results of a final measurement carried out after fabrication, the spare addresses of the spare decoders are programmed, for example, by way of manipulating a ROM or by way of electrically programming floating-gate cells, so that in some cases a considerable increase in yield becomes achievable. After that, however, it is no longer possible to determine or ascertain rows which still have become faulty, and to replace them by redundant rows, because the measuring investment of a final measurement is a quite considerable one.